
Formale Methoden
Formale Verifikation, zugängliche formale Methoden für eingebettete Software, formale Methoden für die Hardware-Verifikation.
Forschende
Prof. Dr. Matthias Güdemann (Hardware Verification, Test Coverage, Model Checking, Software Verification)
Prof. Dr. Stefan Wallentowitz (Open Source Silicon, RISC-V, WebAssembly virtualization, Open Source EDA tools, formal methods for embedded systems)